Toward Robust and Secure AI

As a founding member of the 4-bits/cell NAND flash memory controller team at Samsung Electronics, I delved into the challenges of flash memory reliability—a pivotal research topic. Our team was at the forefront, exploring and developing advanced communication and signal processing algorithms to extend the lifetime of NAND flash memory that laid the groundwork for Samsung's subsequent world-best SSD projects. This experience taught me a valuable lesson about the inherent lifetime limits of semiconductor chips (yes, chips can fail after the lifetime limit).

My passion for semiconductor chip reliability led me to join Professor Chris Kim's research group at University of Minnesota. Professor Kim, an esteemed IEEE fellow and the founding advisor of ANAFLASH, spearheaded groundbreaking research in circuit reliability and silicon lifetime monitoring. I was privileged to contribute to this research, focusing on the silicon odometer—an innovative on-chip reliability monitor. Our findings of PBTI and NBTI induced frequency shifts of the digital circuits in the HKMG CMOS process, were presented at IEEE International Reliability Physics Symposium (IRPS) in 2014. Since then, the silicon odometer aging sensor has been evolved to be synthesizable and open-sourced, fostering further innovation in the field.

In today's era, where cloud providers strive for unparalleled reliability, availability, and serviceability, integrating reliability monitors like the RAS engine in NVIDIA's Blackwell chip represents a critical step forward. Such advancements underscore the importance of proactive failure prediction to maintain continuous service, particularly for generative AI applications without service downtime. As such, it is definitely an interesting research direction to find a solution to extend the chip lifetime further by run-time calibration after the chip is deployed in a field.

At ANAFLASH Inc, we're committed to developing foundational IPs that support secure, reliable chip deployment, leveraging a secure on-chip non-volatile memory technology. Hardware security, a theme I recently pointed out at the edge AI and vision innovation forum, was emphasized again during NVIDIA GTC last week.

I believe collaboration remains critical to advancing reliable and secure AI deployment across edge devices as well as and data center infrastructures. Indeed, Professor Hyeran Jeon advising ANAFLASH at UC Merced, has been conducting robust and secure deep learning computing research and I believe the recently awarded NSF funded research center (CEMSYS) at UC Merced will be poised to contribute significantly to this effort further.

Peter Song, CEO/Co-Founder of ANAFLASH Inc.

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